1. Technical Field of the Invention
The present invention relates to the field of integrated circuit, and more particularly to one-time-programmable memory (OTP).
2. Prior Art
Three-dimensional one-time-programmable memory (3D-OTP) is a monolithic semiconductor memory. It comprises a plurality of vertically stacked OTP cells. In a conventional OTP, the memory cells are formed on a two-dimensional (2-D) plane (i.e. on a semiconductor substrate). In contrast, the memory cells of the 3D-OTP are formed in a three-dimensional (3-D) space. The 3D-OTP has a large storage density and a low storage cost. Because the 3D-OTP has a long data retention (>100 years), it is suitable for long-term data storage.
U.S. Pat. No. 5,838,396 issued to Zhang on Nov. 10, 1998 discloses a 3D-OTP 00. It comprises a semiconductor substrate 0 and a plurality of OTP memory levels 100, 200 stacked above the semiconductor substrate 0. Among them, the memory level 200 is stacked above the memory level 100. Transistors in the substrate 0 and interconnects thereof form a substrate circuit (including the peripheral circuit of the OTP memory levels 100, 200). Each OTP memory level (e.g. 100) comprises a plurality of address lines (e.g. word lines 20a, 20b . . . , and bit lines 30a, 30b . . . ) and memory cells (e.g. 1aa-1bb . . . ). Each OTP memory level 100 further comprises a plurality of OTP arrays. Each OTP array is a collection of all OTP cells which share at least one address line. Contact vias 20av, 30av couple the address lines 20a, 30a with the substrate 0.
The 3D-OTP in Zhang is a single-bit-per-cell 3D-OTP, wherein each 3D-OTP cell stores a single bit. Namely, each OTP cell has two states ‘1’ and ‘0’: the ‘1’ OTP cell is in a low-resistance state, whereas the ‘0’ cell is in a high-resistance state. To further improve the storage density and lower the storage cost, it is desired to store more bits in each 3D-OTP cell.